Physical Design Engineer

CPU Physical Design Engineer (Senior & Staff) - Multiple Headcount - Cambridge (Onsite)

About the Role

Join our world-class CPU team in Cambridge to build next-generation, high-performance, power-efficient custom CPU cores for advanced compute and server platforms. You’ll collaborate with global cross-functional teams (Architecture, RTL, CAD, Circuits, SoC, and Post-Silicon) to push the limits of performance, energy efficiency, and scalability.

Key Responsibilities

• Full-Flow Implementation: Own or contribute to CPU block implementation from RTL/netlist to GDSII (synthesis, floorplanning, placement, CTS, routing, ECOs, and signoff).
• Timing & PPA Closure: Drive timing closure and PPA optimization across demanding modes, corners, and operating conditions.
• Complex Debugging: Resolve complex technical bottlenecks across timing, congestion, IR drop, power integrity, EM, and physical verification (DRC/LVS).
• Methodology & Automation: Enhance physical design flows and automation (TCL, Python, Perl) to boost productivity and design quality.
• Technical Leadership (Staff Level): Lead implementation strategies, mentor engineers, and drive closure on critical CPU blocks or methodology initiatives.

What We’re Looking For

• Core Expertise: Hands‑on experience in high-performance digital ASIC/CPU physical design and Static Timing Analysis (STA).
• EDA Tooling: Proficiency with industry-standard toolsets (e.g., Innovus, Fusion Compiler, PrimeTime, Genus, Tempus, Voltus, RedHawk).
• Scripting: Strong automation skills in TCL, Python, or Perl.
• Education: Bachelor’s, Master’s, or PhD in Electrical/Computer Engineering, Computer Science, or a related field with relevant PD experience.
• Physical design on CPU cores or timing‑critical ASIC blocks on advanced nodes (7nm and below).
• Advanced low‑power techniques, useful skew, power integrity/IR signoff, and late‑stage timing ECOs.

Familiarity with CPU microarchitecture, logic design, or circuit-level tradeoffs.