Senior ASIC Verification Engineer - RSUs & Bonus

IC Resources in Edinburgh is seeking an experienced verification engineer to ensure the functional correctness of complex digital and mixed-signal ASIC designs. You will develop verification plans, build UVM-based testbenches, and drive coverage and regression across full-chip scenarios.

The role requires 5+ years in digital/mixed-signal verification, strong SystemVerilog/UVM skills, and proficiency with Synopsys VCS or Cadence Xcelium.