Senior Design Verification Engineer – Mixed-Signal ASICs

A leading semiconductor company in Edinburgh seeks a Senior Design Verification Engineer to ensure the correctness of complex digital and mixed-signal ASIC designs. The role involves developing verification plans, mentoring engineers, and collaborating with design teams. Candidates should have over 5 years of experience, strong SystemVerilog and UVM skills, and familiarity with ASIC development flows. The position offers competitive salary, RSUs, and flexible work options for UK-based engineers. #J-18808-Ljbffr