Senior FPGA/ASIC Design Engineer for Satellite 5G

We're looking for an experienced Senior Design Engineer to join a team developing cutting-edge communications technology that will help shape the future of global connectivity.

This is an opportunity to work on next-generation 5G non-terrestrial networks developing digital hardware for satellite-based communications systems that will play a key role in delivering worldwide mobile coverage.

Working as part of a highly skilled engineering team, you'll be involved in the design and implementation of high-performance FPGA and ASIC solutions, taking products from architecture through to validation on the latest space-qualified hardware platforms.

Key responsibilities include:

• Translating system and algorithm requirements into RTL micro-architectures
• Designing and implementing RTL using Verilog/SystemVerilog for FPGA and ASIC targets
• Creating testbenches and supporting functional verification
• Deploying and validating designs on FPGA development platforms
• Optimising designs for performance, timing, power, and resource utilisation
• Producing high-quality technical documentation
• Collaborating across architecture, verification, physical implementation, and integration teams
• Contributing to continuous improvement of engineering processes and design methodologies

Skills & Experience

• Strong RTL design experience using Verilog and/or SystemVerilog
• Proven background developing complex FPGA and ASIC designs
• Experience optimising digital hardware for high-throughput signal or data processing
• Knowledge of synthesis, timing analysis, and power optimisation techniques
• Strong understanding of simulation and synthesis using industry-standard EDA tools
• Experience producing technical design documentation
• Excellent collaboration skills with multidisciplinary engineering teams
• Communications or wireless signal processing
• Error correction, channel estimation, equalisation, or beamforming algorithms
• C++ or SystemC modelling
• High-speed interfaces such as PCIe or JESD
• Python or other scripting languages
• ASIC backend flows and implementation tools
• Experience working within Agile or structured hardware development lifecycles