Senior RTL/FPGA Design Engineer for High-Throughput ASICs

Jobtailor in the United Kingdom is seeking an experienced RTL engineer to translate requirements into micro-architectures for FPGA/ASIC implementations. You will deploy designs on FPGA platforms for validation and integrate with the broader design flow.

The role requires expert SystemVerilog/Verilog proficiency, timing optimization, and collaboration across teams. You will document designs, create testbenches, and use modern EDA tools to deliver high-throughput data processing solutions.